This invention relates to power semiconductor devices, and more particularly relates to power semiconductor devices in which a p-n junction, remote from the device surfaces, carries the device operating voltage and field effect gates are used to control the device operation.
Power semiconductors, as distinguished from signal semiconductors, are used to process and control the flow of electric energy supplied to user loads. The utility of such devices is driven by their ability to quickly and efficiently switch on and off large operating voltages and currents. Power semiconductor switching devices are increasingly being designed to handle applications requiring high blocking voltages in the off condition, typically 1 kV and greater, and high current requirements in the on state, typically 1 A and greater. Recent advances in device operating thresholds, however, have imposed operational and fabrication-related problems for power semiconductor devices.
Historically, power semiconductor devices have required large switching currents to handle the corresponding high device currents. Large switching currents result in device inefficiencies since excessive electrical power is required to operate the device. Power semiconductor devices to-date have employed metal-oxide-semiconductor (MOS) gate structures in a variety of arrangements to achieve the low current turn-on and turn-off requirements of these devices. However, MOS gates have experienced operational and fabrication-related reliability problems as the operational boundaries of the power semiconductor devices have been expanded. In particular, the high operating device voltages create large electric fields within these devices, which poses long-term reliability problems for the oxides used in the MOS gates. Trenched MOS gates (UMOS), as found in the paper by A. K. Agarwal et al. entitled SiC Power Device Development given at the All Electric Combat Vehicle (AECV) Second International Conference Jun. 8th-12th 1997, and buried structures, U.S. Pat. No. 5,543,637, have been employed to partially overcome these oxide limitations. In each of these arrangements, however, large electric fields are still present at the oxide interfaces thereby compromising the long-term oxide reliability. Finally, gate oxides are often fabricated on implanted semiconductor regions, which results in low oxide quality and reliability, particularly in power devices fabricated from SiC. An exemplary high-power thyristor device employing such a MOS gate structure can be found in the above article by A. K. Agarwal.
The need exists for monolithic, simply constructed, easily fabricated, power semiconductor devices in which the controlling gate structures are fabricated without oxides or dielectric insulators and are removed from the large electric fields within the device. Although non-oxide gate structures are preferred, the need also exists to provide a reliable, non-implanted semiconductor surface on which to fabricate gate oxides, for those power semiconductors which continue to employ MOS gates, and to isolate such gate oxide from the large electric field stresses.
A preferred embodiment according to the present invention provides for a semiconductor device comprising: (a) a semiconductor structure having top and bottom surfaces, the structure including a plurality of semiconductor layers defining a blocking p-n junction remote from both the surfaces, the structure including a control layer defining the top surface of the structure; a top conductive region extending from the top surface; a conductive tub region spaced apart from the top conductive region and extending from the top surface toward the blocking p-n junction at least through the control layer, the control layer including a field effect region disposed between the top conductive region and the conductive tub region; (b) a top ohmic contact in contact with the top surface at the top conductive region; (c) a bottom ohmic contact in contact with the semiconductor structure below the blocking p-n junction, the semiconductor layers being arranged so that when a potential is sustained between the top and bottom ohmic contacts, a major portion of the potential appears across the blocking p-n junction thereby forming depletion regions about the blocking p-n junction, and (d) a gate contact overlying the field effect region, whereby conductivity of the field effect region can be selectively controlled by a controlling potential on the gate contact to create and interrupt a conductive channel within the control layer, the top conductive region and the conductive tub region being coupled and decoupled by the conductive channel, the conductive tub region extending downwardly to the vicinity of the blocking p-n junction so that a least resistive current path including the top conductive region, the conductive channel and the conductive tub region is created between the top ohmic contact and the blocking p-n junction when the conductive channel is created.
In yet another embodiment, the semiconductor device further comprises a control p-n junction disposed above the blocking p-n junction and remote from the top surface, the gate contact forming a Schottky contact such that the gate contact, the field effect region, the top conductive region and the conductive tub region constitute a MESFET. Alternatively, the semiconductor device may further comprise a control p-n junction disposed above the blocking p-n junction and remote from the top surface, the field effect region having a gate conductive region extending from the top surface under the gate contact toward the control p-n junction such that the gate contact, the gate conductive region, the field effect region, the top conductive region and the conductive tub region constitute a JFET. Alternatively, the semiconductor device may further comprise a control p-n junction disposed above the blocking p-n junction and remote from the top surface, the gate contact including an insulative layer on the top surface and a conductive contact on the insulative layer such that the gate contact, the field effect region, the top conductive region and the conductive tub region constitute a MOSFET. Yet another embodiment includes the semiconductor device in which the top conductive region includes a first subregion of same semiconductor type as the control layer and extending to a first depth from the top surface, a second subregion of opposite semiconductor type from the control layer extending to a second depth from the top surface and disposed between the first subregion and the field effect region, both of the subregions being in contact with the top ohmic contact, the gate contact including an insulative layer on the top surface and a conductive contact on the insulative layer such that the gate contact, the field effect region, the second subregion of the top conductive region and the conductive tub region constitute a MOSFET.
Additional embodiments of the invention include the semiconductor device in which the field effect region includes unimplanted epitaxially grown semiconductor defining the top surface in the field effect region, whereby the insulative layer includes an insulating compound on the unimplanted epitaxially grown semiconductor.
In one preferred embodiment, the semiconductor device may also be arranged such that the semiconductor device is a field controlled transistor, the conductive tub region extending at least to the blocking p-n junction and having a bottom end being disposed in the depletion region of the blocking p-n junction when the potential is sustained between the top and bottom ohmic contacts, the conductive tub region being alternatively depleted and undepleted of carriers in response to the selective controlling potential on the gate contact, whereby the transistor switches xe2x80x9coffxe2x80x9d and xe2x80x9conxe2x80x9d respectively. In this embodiment the semiconductor device may have the top conductive region including a first subregion of same semiconductor type as the control layer and extending to a first depth from the top surface; a second subregion of opposite semiconductor type from the control layer extending to a second depth from the top surface and disposed between the first subregion and the field effect region, both subregions in contact with the top ohmic contact, the gate contact including an insulative layer on the top surface and a conductive contact on the insulative layer such that the gate contact, the field effect region, the second subregion of the top conductive region and the conductive tub region constitute a MOSFET. Alternatively, the semiconductor device further comprises a control p-n junction disposed above the blocking p-n junction and remote from the top surface, the gate contact forming a Schottky contact such that the gate contact, the field effect region, the top conductive region and the conductive tub region constitute a MESFET. Alternatively, the semiconductor further comprises a control p-n junction disposed above the blocking p-n junction and remote from the top surface, the field effect region having a gate conductive region extending from the top surface under the gate contact toward the control p-n junction such that the gate contact, the gate conductive region, the field effect region, the top conductive region and the conductive tub region constitute a JFET. In yet other preferred embodiments, the semiconductor device comprises a control p-n junction disposed above the blocking p-n junction and remote from the top surface, the gate contact including an insulative layer on the top surface and a conductive contact on the insulative layer such that the gate contact, the field effect region, the top conductive region and the conductive tub region constitute a MOSFET.
In an additional preferred embodiment is provided the semiconductor in which the semiconductor device is a field-gated bipolar transistor, the semiconductor structure having a lower p-n junction remote from the top and bottom surfaces and disposed below the blocking p-n junction, the conductive tub region extending at least to the blocking p-n junction and having a bottom end being disposed in the depletion region of the blocking p-n junction when the potential is sustained between the top and bottom ohmic contacts, the conductive tub region being alternatively depleted and undepleted in response to the selective controlling potential on the gate contact, whereby the bipolar transistor switches xe2x80x9coffxe2x80x9d and xe2x80x9conxe2x80x9d respectively. This embodiment may further include a semiconductor device in which the top conductive region includes a first subregion of same semiconductor type as the control layer and extending to a first depth from the top surface, a second subregion of opposite semiconductor type from the control layer extending to a second depth from the top surface and disposed between the first subregion and the field effect region, both subregions in contact with the top ohmic contact, the gate contact including an insulative layer on the top surface and a conductive contact on the insulative layer such that the gate contact, the field effect region, the second subregion of the top conductive region and the conductive tub region constitutes a MOSFET. In another variation, the semiconductor device may further comprise a control p-n junction disposed above the blocking p-n junction and remote from the top surface, the gate contact forming a Schottky contact such that the gate contact, the field effect region, the top conductive region and the conductive tub region constitute a MESFET. In yet another variation, the semiconductor device further comprised a control p-n junction disposed above the blocking p-n junction and remote from the top surface, the field effect region having a gate conductive region extending from the top surface under the gate contact toward the control p-n junction such that the gate contact, the field effect region, the gate conductive region, the top conductive region and the conductive tub region constitute a JFET. In a final variation of this type, the semiconductor device further comprises a control p-n junction disposed above the blocking p-n junction and remote from the top surface, the gate contact including an insulative layer on the top surface and a conductive contact on the insulative layer such that the gate contact, the field effect region, the top conductive region and the conductive tub region constitute a MOSFET.
In an additional preferred embodiment is provided the semiconductor device in which the semiconductor device is a field turn-off thyristor; (a) the top conductive region including a first subregion extending to a first depth from the top surface, and a second subregion extending to a second depth from the top surface and disposed between the first subregion and the field effect region, both subregions in contact with the top ohmic contact; (b) the semiconductor structure having a lower and an upper p-n junction, both remote from the top and bottom surfaces; the lower p-n junction disposed below the blocking p-n junction, the upper p-n junction disposed above the blocking p-n junction, the conductive tub region extending at least through the upper p-n junction; a latch-on gate ohmic contact overlying the conductive tub region at the top surface, whereby when the conductive channel is interrupted, current flow through the conductive tub region can be selectively controlled by a controlling current applied through the latch-on gate ohmic contact to turn on the upper p-n junction and thereby switch xe2x80x9conxe2x80x9d the thyristor; and whereby in an absence of the controlling current on the latch-on gate contact, the controlling potential on the gate contact can create the conductive channel to bypass the upper p-n junction and thereby switch xe2x80x9coffxe2x80x9d the thyristor. In one variation, the semiconductor device has the first subregion of same semiconductor type as the control layer, the second subregion is of opposite semiconductor type from the control layer, the gate contact including an insulative layer on the top surface and a conductive contact on the insulative layer such that the gate contact, the field effect region, the second subregion of the top conductive region and the conductive tub region constitute a MOSFET. In another variation, the semiconductor device further comprises a control p-n junction disposed above the upper p-n junction and remote from the top surface, the first subregion being of opposite semiconductor type from the control layer, the second subregion of same semiconductor type as the control layer, the first depth of the first subregion extending beyond the control p-n junction from the top surface, the gate contact forming a Schottky contact such that the gate contact, the field effect region, the second subregion of the top conductive region and the conductive tub region constitute a MESFET. In yet another variation, the semiconductor device further comprises a control p-n junction disposed above the upper p-n junction and remote from the top surface, the first subregion being of opposite semiconductor type from the control layer, the second subregion of same semiconductor type as the control layer, the first depth of the first subregion extending beyond the control p-n junction from the top surface, the field effect region further comprises a gate conductive region extending from the top surface under the gate contact toward the control p-n junction such that the gate contact, the field effect region, the gate conductive region, the second subregion of the top conductive region and the conductive tub region constitute a JFET. In a final variation of this type, the semiconductor device further comprises a control p-n junction disposed above the upper p-n junction and remote from the top surface, the first subregion being of opposite semiconductor type from the control layer, the second subregion of same semiconductor type as the control layer, the first depth of the first subregion extending beyond the control p-n junction from the top surface, the gate contact including an insulative layer on the top surface and a conductive contact on the insulative layer such that the gate contact, the field effect region, the second subregion of the top conductive region and the conductive tub region constitute a MOSFET.
In additional embodiments of the invention, the semiconductor device includes a semiconductor structure further comprising a blocking layer of relatively low doping concentration disposed below the blocking p-n junction and an enhancement layer of same semiconductor type and relatively higher doping concentration as the blocking layer disposed above the lower p-n junction. Also, the semiconductor device may have the top conductive region including a first subregion of opposite semiconductor type from the control layer and extending through the control p-n junction from the top surface, and a second subregion of the same semiconductor type as the control layer extending to a second depth from the top surface and disposed between the first subregion and the field effect region, both of the subregions in contact with the top ohmic contact. The semiconductor device may also have semiconductor layers composed of a material selected from the group consisting of SiC, Si, Diamond, GaAs, GaN, AlN, AlGaN, InGaN, GaP, AlGaP or AlGaAsP and combinations thereof Additionally, the semiconductor device includes semiconductor layers including a bottom layer, the bottom layer being in contact with the bottom ohmic contact and further including a buffer layer for improving the semiconductor structure quality.
In yet additional embodiments, the semiconductor device has no insulative layer as part of the gate contact. Also, the semiconductor may further comprise a control p-n junction disposed above the blocking An junction and remote from the top surface, the field effect region including an unimplanted portion of the control layer. Also, the semiconductor device may further comprise a control p-n junction disposed above the blocking p-n junction and remote from the top surface; an upper p-n junction disposed between the blocking p-n junction and the control p-n junction. Additionally, the semiconductor device further comprises a lower p-n junction disposed below the blocking p-n junction and remote from the bottom surface. Also, the semiconductor device has the top conductive region including a first subregion of opposite semiconductor type from the control layer extending to a first depth at least through the control layer from the top surface; a second subregion of the same semiconductor type as the control layer extending to a second depth not through the control layer from the top surface and disposed between the first subregion and the field effect region, the first and second subregions being in contact with the top ohmic contact.
In other embodiments, the semiconductor device has the top conductive region including a first subregion of same semiconductor type as the control layer extending to a first depth not through the control layer from the top surface; a second subregion of opposite semiconductor type from the control layer and extends to a second depth, shallower than the first depth, from the top surface and disposed between the first subregion and the field effect region, both subregions being in contact with the top ohmic contact. Also, the semiconductor device may have the conductive tub region extending at least to the blocking p-n junction and has a bottom end disposed in the depletion region of the blocking p-n junction when the potential is sustained between the top and bottom ohmic contacts such that the field effect region is shielded from the potential. The semiconductor device may also further comprise a latch-on gate ohmic contact overlying the conductive tub region at the top surface. Additionally, the semiconductor device may further comprise a lower and an upper p-n junction, both remote from the top and bottom surfaces, the lower p-n junction disposed below the blocking p-n junction, the upper p-n junction disposed above the blocking p-n junction, the conductive tub region extending through the upper p-n junction; a latch-on gate ohmic contact overlaying the conductive tub region at the top surface, the semiconductor layers being of relative conductivity, whereby a latch-on current applied at the latch-on gate ohmic contact, flows through the conductive tub region and laterally beneath the upper p-n junction before traversing the upper p-n junction beneath the top ohmic contact.
In yet another embodiment of the present invention, the semiconductor device further comprises a semi-insulating layer disposed directly beneath the control layer and the field effect region; the conductive tub region extending at least through the semi-insulating layer, whereby the field effect region within the control layer is electrically isolated by the semi-insulating layer from a semiconductor layer directly beneath the semi-insulating layer in a direction perpendicular to the top surface. In variations in this embodiment, the semiconductor device may include the gate contact forming a Schottky contact such that the gate contact, the field effect region, the top conductive region and the conductive tub region constitute a MESFET, or the field effect region further including a gate conductive region extending from the top surface under the gate contact toward the semi-insulating layer such that the gate contact, the gate conductive region, the field effect region, the top conductive region and the conductive tub region constitute a JFET.
Further embodiments of the invention include the semiconductor device in which the conductive tub comprises a part of a blocking layer defining a lower semiconductor layer of the blocking p-n junction, or the semiconductor device in which the conductive tub comprises a part of the control layer, or the semiconductor device in which the conductive tub comprises an ion implanted region. extending from the top surface.
In a preferred method of the present invention, a method is provided for operating a semiconductor device having a plurality of semiconductor layers, a top and bottom surface and including a control layer defining the top layer of the device, the method comprising the steps of: (a) applying a voltage between a top and a bottom ohmic contact of the semiconductor device; (b) sustaining the voltage across a blocking p-n junction defined by the semiconductor layers and remote from the top and bottom surfaces; (c) selectively creating or interrupting a conductive channel in the control layer between a top conductive region, disposed below the top ohmic contact, and a tub conductive region, spaced apart from the top conductive region and extending at least to the blocking p-n junction, by applying a control potential to a gate contact disposed over the control layer so as to cause a least resistive path including the top conductive region, the conductive channel and the conductive tub region to be created between the top ohmic contact and the blocking p-n junction when the conductive channel is created.
In another preferred method, a method is provided for operating a semiconductor device having a plurality of semiconductor layers, a top and bottom surface and including a control layer defining the top layer of the device, the method comprising the steps of: (a) applying a voltage between a top and a bottom ohmic contact of the semiconductor device; (b) sustaining the voltage across a blocking p-n junction defined by the semiconductor layers and remote from the top and bottom surfaces; (c) selectively applying a control current to a latch-on gate contact disposed over a tub conductive region, the tub conductive region extending through an upper p-n junction defined by the semiconductor layers and remote from the top and bottom surfaces, the upper p-n junction being disposed above the blocking p-n junction and being selectively turned on when the control current is selectively applied to the latch-on gate; (d) selectively creating or interrupting a conductive channel in the control layer between a top conductive region, disposed below the top ohmic contact, and a tub conductive region, spaced apart from the top conductive region and extending through the upper p-n junction, by applying a control potential to a gate contact disposed over the control layer so as to selectively short-circuit the upper p-n junction when the conductive channel is created thereby turning off the thyristor semiconductor device.